| Summary: | 碩士 === 元智大學 === 通訊工程學系 === 101 === In recent years, along with the development of vehicle wireless communication technology, the dedicated short range communication (DSRC) has become the core technology on which the intelligent transportation systems (ITS) relies. In addition, the protocols of IEEE802.11p and IEEE1609 have also been applied to the DSRC system.
In this thesis, by referring the national CNS standard of electrical toll collection, the frame synchronization of DSRC is designed. Through the frame synchronization, the receiver can determine the frame start and end by using a series of data information. The designed frame synchronization circuit is simulated and verified by using Verilog, Quartus II, and ModelSim. In addition, the Verilog code is implemented on an FPGA platform, which shows the consistence with our design.
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