Ultra Low Power Array Multiplier Based on Modified NAND Full Adder Scheme in Sub-threshold Region

• Main Authors: Cheng-kai Chang, 張仲凱
• Other Authors: Ming-hwa Sheu
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/63276436306550699952

碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 101 === In recent years, with the rapid evolution of VLSI process technology, many portable electronic products such as medical / biomedical electronic devices, wireless sensing element and smart-phones etc are constantly being designed and implemented. These products are required low voltage and low power consumption. How to reduce the operating voltage and power dissipation becomes the main design consideration in engineering. Based on the formula of the power consumption, the supply voltage can be decreased to reduce power dissipation effectively. For this reason, the circuit design for ultra low voltage could operate in the sub-threshold region. Under the threshold voltage, pMOS characteristics will become degradation. Therefore the pMOS series affect the performers of whole circuit. So the full adder is composed by using NAND gate such that all pMOS are designed in parallel. Afterward we use the adder to make up a 8x8 array multiplier. Our ultra low-voltage multiplier is implemented and fabricated based on TSMC-1P6M 0.18μm CMOS process to verify the circuit performance. From the simulation results, the minimum operating voltage of our design is at 170mV. Its supply voltage has 39% and 11% lower than those of traditional 28T and TGA designs respectively. In addition, the process variation is also considered in our design. Finally, the chip measurement can reach to 100mV with 1KHz working frequency.