High-efficiency high-voltage DC/DC step-down chip design
碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 101 === In this thesis, it uses the process of TSMC 0.25 um CMOS HIGH VOLTAGE MIXED SIGNAL to complete a total of three wafers and be off the assembly line of TSMC through CIC. The wafers are as the following respectively: (a) low-dropout linear regulator. Measu...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/36796732916723368848 |