Design of Low Power and Low Phase Noise CMOS VCO Based on Current Reused Topology with Current-Shaping Technique and Double Tuning Technique for Phase Locked Loop Application

• Main Authors: Cheng-Chuan Chung, 鍾政全
• Other Authors: none
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/50018218909093040996

碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 101 === The fast-growing market in wireless communications requires small, cheap, wide band, low phase noise and low power RF circuits. The major challenge lies in the design of fully integrated low phase noise and low power voltage controlled oscillators (VCOs) with appropriate tuning range performance simultaneously. The voltage-controlled oscillator (VCO) is one of the most important building blocks in the system. The chip fabrication of VCO is made by TSMC 0.18μm 1P6M CMOS standard process. The first chip presents a low power and low phase noise voltage controlled oscillator (VCO) for IEEE 802.11a applications, the Current-Reused and tail transistor technology is designed to improve phase noise and power. The measured results exhibited phase noise -119.9 dBc/Hz at 1MHz offset frequency, Measured tuning range is about 19.1% from 5.2 GHz to 6.3 GHz and power dissipation is 1.8 mW. The second chip presents a low power voltage controlled oscillator (VCO) for IEEE 802.11a applications, the Current-Reused and self-body bias technology is designed to improve power. The measured results exhibited phase noise -114.63 dBc/Hz at 1MHz offset frequency, Measured tuning range is about 16% from 5.15 GHz to 6.05 GHz and power dissipation is 0.8 mW.