CMOS Building Blocks Design for GHz Phase-Locked Loops

CMOS Building Blocks Design for GHz Phase-Locked Loops

碩士 === 國立雲林科技大學 === 電子與光電工程研究所碩士班 === 101 === A high-speed CMOS 1/2 frequency divider is presented. Using fewer transistors and only N-type MOS transistors in the regenerative circuits of the latches, the frequency divider achieves higher speed through the reduced capacitances at the output nodes an...

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Bibliographic Details
Main Authors:	Chao-Yuan Su, 蘇昭源
Other Authors:	none
Format:	Others
Language:	zh-TW
Published:	2013
Online Access:	http://ndltd.ncl.edu.tw/handle/41505508972887326545

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