| Summary: | 博士 === 淡江大學 === 電機工程學系博士班 === 101 === As test data volumes continue to grow, test costs also increase. To lower test costs, this paper presents a new compression method for testing large circuits, based on multiple scan-chains and an unknown structure. This method is targeted at intellectual property (IP) cores and system-on-a-chip (SoC) circuits. This study considers the shift-in power and compression ratio in low-cost ATE environments.
This study presents a new compression architecture with fixed length for testing large circuits. Because power-aware test data are not changed frequently, a selector is used to filter the unnecessary status, and buffers are used to hold the back data. A new algorithm is proposed to assign multiple scan-chains. An improved linear dependency compute method is also proposed to determine the hidden dependency between scan-chains. Experimental results show that the proposed method can reduce both test data volume and shift-in power.
The results showed that when the VLSI circuit grows in complexity, number of input pins required for testing increases slowly. The average compression ratio of the proposed method was 63% for MinTest and TetraMAX. On ISCASce for both tests, a value of 3x/6.6x was observed for MinTest and 2.3x/5.6x for TetraMAX, after comparing Selective Scan Slice (SSS) with the proposed method. The averages of hardware overhead costs were 6% for MinTest and 6.5% for TetraMAX.
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