| Summary: | 碩士 === 國立臺北科技大學 === 電腦與通訊研究所 === 101 === In recent year, task placement in reconfigurable FPGA have been developed into 2-D reconfigurable space and the tasks are configured into 2-D array. In this work, we solve the task type placement problem for partial dynamic reconfigurable system. We and propose a pre-place hardware resource into multi-area methodology to achieve high utilization of hardware resource. The proposed placement method can provide each requested task module loading into pre-place reconfigurable area. In this experiment, the tool of Xilinx PlanAhead 14.1 is used to analyze the task placement in the configuration area and the Xilinx Virtex-6 development platform is used to verify the system function. According to experiment results show that the proposed Regional-Based Task Placement(RBTP) methodology, under using DSP task module can improve 30.28% hardware resources on utilization, and reduce 48.89% the area of hardware resources. On non-DSP task module case, the proposed method can improve 21.26% hardware resources on utilization, and reduce 35.73% the area of hardware resources.
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