| Summary: | 碩士 === 國立臺北科技大學 === 機電整合研究所 === 101 === Recently, the incorporation of nitrogen (N) in HfO2 gate dielectrics in the annealing process has heavily applied in the advanced MOSFETs because of decreasing equivalent oxide thickness (EOT), improving the breakdown characteristics, and increasing thermal stability. However, only few literatures concerned about negative BTI with decoupled plasma nitridation (DPN) process. Hence, this study is focused on this subject.
The experimental devices were fabricated from 28nm node high performance logic technology of United Micro-electronics Corporation (UMC). The process of HfZrOx dielectric layer was deposited by atomic layer deposition (ALD). The wafers were then annealed with different annealing temperatures and nitrogen concentrations after ALD. In this research, the different experimental temperatures and stress voltages are included in the experiment. Consequently experimental data are used to figure out the dependence of degradation on stress voltage, and to determine the difference of four kinds of wafers.
The experimental results of this work indicated that the pMOSFETs under the highest annealing temperatures (900℃) have the largest drain current because of the high annealing temperatures may repair defects in the gate dielectrics. After the NBTI stress, the degradation at those high experimental temperatures reveal larger than that at low experimental temperatures. Moreover, no matter what in high or low temperature, or under different negative bias is, the pMOSFETs with 8% nitrogen 700℃ annealed conditions exhibit the minimal degradation. However, even if the pMOSFETs with 8% nitrogen 900℃ have the best initial performance, but they have worse reliability than other devices.
|
|---|
