Design of Low-Power Reference Voltage

• Main Authors: Jia-Hao Shih, 施家豪
• Other Authors: 劉偉行
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/q3kxxf

碩士 === 國立虎尾科技大學 === 電子工程系碩士班 === 101 === In this thesis, two low-power differential-mode reference voltage circuits have been proposed. The design principle is based on the low-power dissipation characteristic and the exponential relationship between the voltage and the current of the MOSFET in sub-threshold region, When the NMOS transistor is operating in the sub-threshold region, appropriately adjust the positive and negative temperature coefficients, a zero temperature coefficient reference voltage circuit can be realized. As compared with the existed differential mode reference voltage circuit, the proposed circuit benefits from low-power consumption, simpler circuit architecture, and less chip area. In this thesis, detailed design principle has been disclosed, also the HSPICE and LAKER simulation program with 0.35-um and 0.18-um process parameters have been used to do the pre-layout and post-layout simulation. According to the post-layout simulation results, under the supply voltage of 1.8V, the first proposed improved CMOS reference voltage circuit shows that, as the temperature varies from -20oC to 120oC, the corresponding output voltage changes only 2mV, the power dissipation is only 4.5959uW and the temperature-coefficient is 18.40 ppm/˚C. The simulation results of the second proposed reference voltage circuit shows that, under the supply voltage of 2.1V, the temperature is varies from -20˚C to 120˚C, the output voltage changes 3mV, the power dissipation is only 21.516uW and the temperature coefficient is 29.22 ppm/˚C. Both the simulation results are consistent with the theoretic analysis. The proposed circuit can be applied to medical instruments and other analog circuits.