Power and Signal Integrity Optimization Design of System in Package using Inverter Chip
碩士 === 國立高雄大學 === 電機工程學系碩士班 === 101 === The system voltage noise tolerance decreases in wafer process technology by high frequency, high-speed and low-power development. In the past, adding cost of waste capacitors to optimize in PCB. In this paper, design the Ball Grid Array substrates by package d...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/82853857128824437349 |