| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 101 === This thesis is researching a cascaded dual-loop delta-sigma modulation fractional-N frequency synthesizer for long term evolution applications. From the literature, we can know that the long term evolution’s frequency ranges of Japan, Europe, United State and China which are covering from 788 MHz to 862 MHz and 1.9 GHz to 2.6 GHz, so we designed the output frequency ranges of this fractional-N frequency synthesizer are six times or two times of the above frequencies (3.8 GHz ~ 5.2 GHz).
This cascaded dual-loop fractional-N frequency synthesizer is design in the TSMC 0.18μm CMOS process, the supply voltage is 1.8 V and 1.2 V, chip area is 1.736 mm2 and the total power consumption is 71.51 mW. The synthesizer’s first loop is produced by the injection-locked frequency multiplier which can produce 8 times frequency of crystal oscillator, by using first loop’s high output frequency as second loop’s reference frequency, the second loop’s divide ratio can be reduced then the output in-band phase noise of this synthesizer can be reduced to -90 dBc/Hz@100 kHz, out-of-band phase noise is -117.0 dBc/Hz@7.5 MHz, also due to high reference, quantization noise of delta-sigma modulation can be pushed to much higher frequency, thus output phase noise will not be impacted by quantization noise more.
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