A Digital Phase-Locked Loop with Novel Frequency Estimation and Phase Error Compensation
碩士 === 國立臺灣科技大學 === 電機工程系 === 101 === This thesis presents a frequency estimation method and a phase-frequency compensation mechanism for an all digital phase-locked loop (ADPLL). First, a novel digital-controlled oscillator (DCO) was designed. This DCO possesses good linear relation between control...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/76151611310062650826 |