Fabrication and Investigation of IGZO TFT with Novel Structure Using Self-Align Process and its Reliability

• Main Authors: Bo-Jyun Li, 李柏軍
• Other Authors: Ching-Lin Fan
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/05789841386473811256

碩士 === 國立臺灣科技大學 === 光電工程研究所 === 101 === Metal oxide thin-film transistor (TFT) is generally using bottom-gate and top-contact structure to prevent the effect of backlight of liguid crystal display (LCD) on the electrical performance of TFT. In bottom-gate structure, the drain and source (S/D) electrodes are designed to have a coverage area up the gate electrode to take into account the alignment error; however, this coverage area can create the parasitic capacitance to affect the operation speed of TFT. 　　We proposed a novel structure that is using self-align process to reduce the parasitic capacitances between the gate and the S/D electrodes. Furthermore, we investigated the effect of reduced parasitic capacitance on TFT performance using transmission line method (TLM), capacitance-to-voltage (C-V) measurement, and the rise-time of fabricated inverter measurement. 　　In addition, we performed investigation of a Teflon/SiO2 bilayer passivation on the stability of TFT that is using the proposed self-align structure. The Teflon was deposited as a buffer layer using a thermal evaporator, and it exhibited good compatibility with the underlying a-IGZO layer. The Teflon as buffer layer can effectively protect the a-IGZO TFTs from plasma damage during the sequent SiO2 passivation process. The stability of TFT was studied with various ambient condition and various bias stress.