Research of K-band CMOS Transformer Combined Power Amplifier With 3-D Architecture and Efficiency Enhancement Technique

• Main Authors: Yu-Feng Hsiao, 蕭淯方
• Other Authors: Tian-Wei Huang
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/15253413046392828272

碩士 === 國立臺灣大學 === 電信工程學研究所 === 101 === With the development of wireless communication, the radial frequency integrated circuit with CMOS technology is valued gradually in the industry. Among the transceiver, power amplifier is the most critical component. As the reasons, the design and analysis of CMOS power amplifier is focused in this thesis. In chapter 2, an ultra-compact 24-GHz power amplifier implemented in 180-nm CMOS process. For compact chip size design, transformers are adopted to accomplish the functions of power combining, impedance matching and single-to-differential ended simultaneously. A virtual ground is generated at the symmetry of circuit by push-pull topology. DC bias can be fed directly without large value bypass capacitors, and the chip size is further reduced. The power amplifier achieves the smallest chip size 0.26 mm2 and the highest area efficiency around 24-GHz. In chapter 3, a K-band high output power transformer combined power amplifier with 3-D architecture implemented in 65-nm CMOS process. In order to achieve high output power, 8-ways power combining is realized by the radial splitter and radial combiner. The radial networks with the function of impedance transformation to alleviate the loss of input and output matching networks caused by large impedance transformation ratio. Thanks to the radial structure, the power splitter and power combiner can share the center area of the circuit by a 3-D architecture, therefore the area occupied by power splitter and power combiner can be reduced significantly. The power amplifier achieves the highest saturated output power 26.1 dBm with excellent area efficiency at K-band. In chapter 4, a 2-GHz Doherty power amplifier implemented in 180-nm CMOS process. All passive elements with λ/4 topology are fabricated off-chip on FR-4 board to diminish the chip size and mitigate the loss caused by elements to improve efficiency. The power amplifier performs 20% PAE and maintains 19% PAE at 6 dB power back-off.