Design of Continuous-Time Delta-Sigma Modulators with SAR Quantizers Employing Noise-Shaping Concept

• Main Authors: Bi-Ching Huang, 黃必青
• Other Authors: 林宗賢
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/79404175661356201193

碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === This thesis consists of two works. The first work is a low-power continuous-time delta-sigma modulator (CTDSM), which consists of a 3rd-order feed-back and feed-forward combined loop filter structure, a 5-bit quantizer with 2 bits truncated by a truncator and embedded with a noise-shaping mechanism. The second work presents a CTDSM with a 2nd-order feed-forward loop filter structure and a 3-bit noise-shaped SAR quantizer, leading to an equivalent 3rd-order noise shaping, which improves the overall resolution of the modulator. A 5-bit, low-power CTDSM embedded with a noise-shaped and truncated SAR quantizer is proposed in the first work. The bit truncation reduces the number of feedback DAC cells and relaxes the implementation of DEM circuit while the delay introduced by the 2-LSB signal is swallowed by the truncation process. Implemented in a 90-nm CMOS process, the measured performance shows a peak SNDR of 67.23 dB over a signal bandwidth of 1.92 MHz with 61.44 MHz sampling frequency. This modulator consumes a total power of 2.25 mW, resulting in an FoM of 312 fJ/Conversion-Step. A low-power CTDSM with a 3-bit noise-shaped SAR quantizer is studied in the second work. The noise-shaped quantizer gives an extra-order of noise shaping to the modulator, resulting in a 3-bit 3rd-order delta-sigma modulator. This modulator was realized in a 0.18-um CMOS technology. Under a power supply of 1.8 V and a sampling frequency of 32 MHz, the measured performance shows a peak SNDR of 70.23 dB over a signal bandwidth of 1 MHz and an FoM of 470 fJ/Convsion-Step. The modulator consumes a total power of 2.47 mW.