A Single-channel, 1.2GS/s, 6-bit, 2-bit/cycle SAR ADC

• Main Authors: Sheng-Wei Lin, 林昇緯
• Other Authors: 陳信樹
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/29709209576457803123

碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === A single channel, asynchronous, 6-bit successive approximation ADC with 1.2GS/s, in 40nm CMOS technology is proposed. In this design, the 2-bit/cycle technique is used. Compared with the previously 2-bit/cycle, this architecture uses just three capacitor arrays to reduce the hardware and power consumption. In this work, single-channel, 1.2GS/s is achieved. This design uses the body capacitance foreground calibration in order to reduce the comparator offset voltage. The measurements are performed with different supplies, in order to test the chips’ maximum performance of conversion rate. The SAR ADC can reach 1GS/s with a 1V supply, consuming 4.08mW. And it reaches 1.2GS/s with a 1.1 supply voltage, consuming 6.2mW. At 1GS/s, the peak signal to noise and distortion ratio is 34.75dB. When the sampling rate is increased to 1.2GS/s, the peak signal to noise and distortion ratio is 34.66dB. The ADC occupies an active area of 0.016 mm2, and whole chip with pads occupies 0.39 mm2.