A Single-channel, 1.2GS/s, 6-bit, 2-bit/cycle SAR ADC
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === A single channel, asynchronous, 6-bit successive approximation ADC with 1.2GS/s, in 40nm CMOS technology is proposed. In this design, the 2-bit/cycle technique is used. Compared with the previously 2-bit/cycle, this architecture uses just three capacitor arrays...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29709209576457803123 |