A 1.47ps Low Jitter, 120MHz – 1.4GHz Wide-Range, and Fast-Locking All-Digital Delay-Locked Loop

• Main Authors: Wei-Hao Kao, 高偉浩
• Other Authors: Chung-Ping Chen
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/85571250698167373520

碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === In recent years, the trend of IC design goes toward to the system-level and single-chip solution. Therefore, we usually integrate many intellectual properties (IPs) and customized blocks into a single chip, named System-on-Chip (SoC). As a result, the DLLs are usually used to synchronize the timing of the whole system. However, the analog DLLs are more difficult to be implemented and designed in the advanced process nowadays, and suffered from the PVT variations. On the contrary, the digital DLL circuits are simpler and easier for implementation over technologies. Recently, since the demand of memory market increases, the digital DLL is required to have low jitter and wide operating frequency range. Besides, the characteristic of the fast-locking is also important, since some systems have to be synchronized very quickly after the sleep mode. As a result, a wide-range, low jitter, and fast-locking all-digital DLL is proposed in this work. In this thesis, a novel coarse-tune phase generator (CTPG) is proposed to replace the conventional digital-controlled delay line used in the all-digital delay-locked loop. The proposed CTPG not only expands the operating frequency range which is from 120MHz to 1.4GHz but also has the characteristic of fast-locking. The proposed ADDLL achieves a fast-locking time in 7-8 clock cycles irrelevant to input frequency. Besides, the closed-loop architecture and the finite state machine (FSM) implemented to avoid the bubble in the digital control code achieve low jitter, which is 1.47ps at 1.4GHz. The chip was fabricated in the TSMC 90nm CMOS process and occupied 0.785 mm2 active area.