A Synchronization-Function-Based TLM Approach for Parallel Multi-Core Instruction-Set Simulations

• Main Authors: Pai, Hsien-Lun, 白憲倫
• Other Authors: Tsay, Ren-Song
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/83045604209667892683

碩士 === 國立清華大學 === 電機工程學系 === 101 === We describe a highly efficient transaction-level modeling (TLM) technique for parallel Multi-Core Instruction-Set simulations (MCISS). We set all the calls of synchronization functions—which dictate interactions among applications on different CPU cores—as the transaction boundary. Using a generic blocking/non-blocking send/receive modeling approach for synchronization functions and proper timing synchronization, we can precisely determine the temporal order of each transaction and hence efficiently calculate accurate simulation results. Our experiments show that the proposed approach attains a simulation speed of up to 549 MIPS, which is three times faster than the state-of-art shared-variable-access approach while producing accurate timing and functional results equal to those from cycle-accurate approaches.