Design and Implementation of a Power-Efficient Stage-Shared Switched-Opamp ΔΣ Modulator with Built-In Choppers for Biomedical Applications
碩士 === 國立清華大學 === 電機工程學系 === 101 === This thesis presents a one-bit third-order discrete-time delta-sigma modulator (DT-ΔΣM) using standard 0.18-μm CMOS process. Switched-opamp (SO) technique is utilized to deal with low supply constraint of sub-1-V operation. The cascade of resonators with distribu...
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| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/5q5kgc |
| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 101 === This thesis presents a one-bit third-order discrete-time delta-sigma modulator (DT-ΔΣM) using standard 0.18-μm CMOS process. Switched-opamp (SO) technique is utilized to deal with low supply constraint of sub-1-V operation. The cascade of resonators with distributed feedforward (CRFF) architecture reduces the signal swings of integrators, alleviating the requirement of high slew rate OTAs at low-power operation. A novel chopper-embedded OTA implemented in the first stage effectively eases the impact of component mismatches and suppresses the 1/f noise. The second and third stages share a single OTA. The stage-sharing concept also leads to a smaller die size and a higher power-efficiency.
Operated at 0.7-V supply voltage with 2.56 MHz sampling rate, the proposed modulator achieves 78 dB peak SNDR over a signal bandwidth of 10 kHz with an OSR of 128 and a power dissipation of only 39 μW. The resultant Figure-of-Merit (FoM) is 299 fJ/conversion-step. The proposed SS-SO ΔΣ ADC is suitable for low-power, high-resolution applications like wireless portable devices and bio-signal acquisition.
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