Body Area Network - Human Body Communication

• Main Authors: Kao, Yu-Han, 高鈺涵
• Other Authors: Ma, Hsi-Pin
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/06175513352074509671

碩士 === 國立清華大學 === 電機工程學系 === 101 === Body area network (BAN) is a solution for wearable personal entertainments and wearable healthcare. BAN is a wireless and short-range communication system. The human body communication (HBC) is one of the transmission technologies of BAN. HBC achieves low power consumption, high data rate and operating with good signal-to-noise ratio (SNR). In this thesis, we propose a transceiver of HBC and introduce the human body channel. The HBC system uses the electric field communication technology to transmit signal through human body. The human body channel is similar to a band-pass filter from 1 MHz to 100 MHz and a conductor which has 300 to 500 times better permittivity than air. Hence, human body is used as a transmission medium and is discussed in two parts. The frequency response which includes the change of amplitude and phase. And the noise characteristics which includes 60 Hz power-line noise and interferences of other devices. The proposed design of HBC system employs the bandwidth from 18.375 MHz to 23.625 MHz and supports the frequency selective (FS) spreader modulation scheme with maximum data rate of 1.3125 Mbps. The whole system is operating in 42 MHz frequency clock and 21 MHz frequency center. The transmitter uses the frequency selective digital transmission(FSDT) scheme so it doesn’t need mixer and RF device. The receiver contains packet detection, sample point detection, timing synchronization and clock drift synchronization with 84 MHz sampling rate. Functional simulations and experiments show the validity of these algorithms and system performance of the proposed transceiver. Under AWGN noise and the channel of experiment result scenario, the simulation results show that the packet error rate(PER) is less than 10−2 in SNR -1.8 dB with a payload of 128 octets and 1.3125 MHz data rate. The architecture and logic design of proposed receiver are also presented. The functionality of proposed logic design is verified by FPGA emulation.