Design of RF CMOS Power Amplifiers using Power Combining Approach

碩士 === 國立清華大學 === 電子工程研究所 === 101 === Abstract The goal of the thesis is to design and implement RF power amplifiers in CMOS technology. The thesis consists of three parts. The first part introduces the basics of power amplifier theories and some common design techniques. In the second part, three p...

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Main Authors: Chan, Chin-Tung, 詹欽棟
Other Authors: Hsu, Shuo-Hung
Format: Others
Language:en_US
Published: 2013
Online Access:http://ndltd.ncl.edu.tw/handle/65169271015920526583
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spelling ndltd-TW-101NTHU54280462015-10-13T22:30:11Z http://ndltd.ncl.edu.tw/handle/65169271015920526583 Design of RF CMOS Power Amplifiers using Power Combining Approach 互補式金氧半導體之功率結合功率放大器之研製 Chan, Chin-Tung 詹欽棟 碩士 國立清華大學 電子工程研究所 101 Abstract The goal of the thesis is to design and implement RF power amplifiers in CMOS technology. The thesis consists of three parts. The first part introduces the basics of power amplifier theories and some common design techniques. In the second part, three power amplifiers (PAs) are designed for 24-GHz systems and implemented in a LP 90-nm CMOS technology. The first PA adopts high efficient transformers to improve maximum power-added-efficiency (PAE). This PA achieves a measured saturated output power (P_sat) of 15.2 dBm, an output 1-dB compression point (P_1dB) of 10.7 dBm, a power-added-efficieny (PAE) of 17.4%, and a linear gain of 10.5 dB at 25 GHz, with a chip size of 0.975 × 0.71 〖mm〗^2. The second PA utilizes flip-chip configuration to assist heat dissipation. This PA achieves a simulated P_sat of 13.4 dBm, a P_1dB of 11.3 dBm, a PAE of 12.7%, and a linear gain of 10.3 dB at 24 GHz, with a chip size of 0.82 × 0.71 〖mm〗^2. Finally, the third K-band PA with the proposed adaptive-bias technique is fabricated. According to the simulation, the proposed PA consumes 367 mW at quiescent state and offers 20.5% PAE at the P_1dB. The PA achieves a simulated P_sat of 22.3 dBm, a P_1dB of 20.5 dBm, a PAE of 24.9%, and a linear gain of 23.4 dB at 24 GHz with the chip size of 1 × 0.74 〖mm〗^2. In the third part, a 77-GHz PA is implemented in a LP 90-nm CMOS technology. The PA achieves a measured P_sat of 13.2 dBm, a P_1dB of 7.6 dBm, a PAE of 2.4% , and a linear gain of 2.4 dB at 77 GHz. The chip size is only 0.63 × 0.5 〖mm〗^2 including all of the testing pads. The simulation results agrees well with the measurement results for the PAs. In addition, all of the PAs demonstrate high performance compared with the prior arts of the CMOS PAs operating at the frequencies at 24 GHz and 77 GHz. Index Terms –CMOS, Power amplifier, K-band, W-band, RF amplifier, Monolithic microwave integrated circuit (MMIC). Hsu, Shuo-Hung 徐碩鴻 2013 學位論文 ; thesis 106 en_US
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language en_US
format Others
sources NDLTD
description 碩士 === 國立清華大學 === 電子工程研究所 === 101 === Abstract The goal of the thesis is to design and implement RF power amplifiers in CMOS technology. The thesis consists of three parts. The first part introduces the basics of power amplifier theories and some common design techniques. In the second part, three power amplifiers (PAs) are designed for 24-GHz systems and implemented in a LP 90-nm CMOS technology. The first PA adopts high efficient transformers to improve maximum power-added-efficiency (PAE). This PA achieves a measured saturated output power (P_sat) of 15.2 dBm, an output 1-dB compression point (P_1dB) of 10.7 dBm, a power-added-efficieny (PAE) of 17.4%, and a linear gain of 10.5 dB at 25 GHz, with a chip size of 0.975 × 0.71 〖mm〗^2. The second PA utilizes flip-chip configuration to assist heat dissipation. This PA achieves a simulated P_sat of 13.4 dBm, a P_1dB of 11.3 dBm, a PAE of 12.7%, and a linear gain of 10.3 dB at 24 GHz, with a chip size of 0.82 × 0.71 〖mm〗^2. Finally, the third K-band PA with the proposed adaptive-bias technique is fabricated. According to the simulation, the proposed PA consumes 367 mW at quiescent state and offers 20.5% PAE at the P_1dB. The PA achieves a simulated P_sat of 22.3 dBm, a P_1dB of 20.5 dBm, a PAE of 24.9%, and a linear gain of 23.4 dB at 24 GHz with the chip size of 1 × 0.74 〖mm〗^2. In the third part, a 77-GHz PA is implemented in a LP 90-nm CMOS technology. The PA achieves a measured P_sat of 13.2 dBm, a P_1dB of 7.6 dBm, a PAE of 2.4% , and a linear gain of 2.4 dB at 77 GHz. The chip size is only 0.63 × 0.5 〖mm〗^2 including all of the testing pads. The simulation results agrees well with the measurement results for the PAs. In addition, all of the PAs demonstrate high performance compared with the prior arts of the CMOS PAs operating at the frequencies at 24 GHz and 77 GHz. Index Terms –CMOS, Power amplifier, K-band, W-band, RF amplifier, Monolithic microwave integrated circuit (MMIC).
author2 Hsu, Shuo-Hung
author_facet Hsu, Shuo-Hung
Chan, Chin-Tung
詹欽棟
author Chan, Chin-Tung
詹欽棟
spellingShingle Chan, Chin-Tung
詹欽棟
Design of RF CMOS Power Amplifiers using Power Combining Approach
author_sort Chan, Chin-Tung
title Design of RF CMOS Power Amplifiers using Power Combining Approach
title_short Design of RF CMOS Power Amplifiers using Power Combining Approach
title_full Design of RF CMOS Power Amplifiers using Power Combining Approach
title_fullStr Design of RF CMOS Power Amplifiers using Power Combining Approach
title_full_unstemmed Design of RF CMOS Power Amplifiers using Power Combining Approach
title_sort design of rf cmos power amplifiers using power combining approach
publishDate 2013
url http://ndltd.ncl.edu.tw/handle/65169271015920526583
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