A More Accurate and High Voltage Real-time Capacitor Monitor Circuit for Potential TDDB Testing

• Main Authors: Chou, Tsung-Hsing, 周宗興
• Other Authors: Chang, Mi-Chang
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/69167503869675779681

碩士 === 國立清華大學 === 電子工程研究所 === 101 === The interconnect line width and spacing shrink with advanced technology. The reduction in line space increases the electric field in the dielectric between metal lines. Thus, time dependent dielectric breakdown (TDDB) needs to be investigated and resolved before the technology is fully qualified. Before the dielectric is completely breakdown, leakage current has been observed to increase (soft breakdown). During this time, the interconnect capacitance (Cmom) might have been changed. But, there is no good way of measuring the capacitance during soft breakdown. Yang has proposed a 4T differential ring oscillator as a real time capacitor monitor circuit [1] with high sensitivity. It magnifies the oscillation frequency change due to capacitance change with Miller effect. But the absolute capacitance is unknown using this method. Besides, it is desirable to observe soft breakdown in shorter time by higher voltage stress, but the I/O MOSFET might be unavailable while technology is in development. An accurate capacitance measurements method under process variation and higher voltage stress using core MOSFET circuit are presented in this thesis. For accurate measurement, the slope matching method is proposed to eliminate process variation using external reference capacitors (Cext). The Cext is connected to the output ports of differential pair. And the Cmom is connected in the same except with additional transmission gates on both ends. The slopes (dT/dC) for Cmom and Cext should be very close to each other if transmission gate is properly designed. Using two or more external reference capacitors provide reference slope (ΔTCext/ΔCext). And ΔTCmom is measured during TDDB soft-breakdown. ThusΔCmom is found by reference slope and measured ΔTCmom. The circuit design is based on TSMC 65LP technology. The core MOSFET based monitor circuit provides higher (2xVDD) stress on the target capacitor without gate oxide overstress. The circuit consists of proposed differential pair, two types of peripheral circuit, cascode core transmission gate and its control circuit. If the I/O MOSFET is taken into consideration, there are five types of monitor circuit. For easy observation, the sensitivity should be high. For accurate measurement, the slope offset of Cmom/Cext should be small. In the end, the best type of monitor circuit is chosen with highest (sensitivity/slope offset) under five corner simulations.