| Summary: | 博士 === 國立清華大學 === 電子工程研究所 === 101 === This dissertation proposes three types of new novel differential nonvolatile memory (NVM) cells for advanced embedded system on a chip (SOC) applications. The novel NVM cells with differential read function were fabricated by fully complementary metal–oxide–semiconductor (CMOS) logic compatible processes or existing NVM technologies, so that their feasibility and performance are comparable to the current industrial NVM solutions. Moreover, the floating gate (FG) data retention performance can be enhanced by the differential read operation, which has a double read window. Further, in addition to the logic-compatible NVM cells, a logic-compatible high voltage device which can realize a fully logic-compatible NVM module for embedded systems was also proposed.
First, two fully logic-compatible multiple-time programmable (MTP) floating gate NVM cells with differential read operations are proposed. Then, in order to realize a fully logic-compatible NVM module for embedded systems, a high voltage contact gate metal–oxide–semiconductor field-effect transistor (MOSFET) with fully logic-compatible process was also proposed.
In addition, a new high-density differential split-gate flash memory cell with self-recovery function is proposed. Since the cell process and tip erase structure are totally inherited from the proven split-gate flash technology, the highly efficient program and erase performances are retained in the new cell. However, data retention and endurance capability are much improved by the new built-in self-recovery function with differential read operation.
In summary, several data retention performance enhancement solutions based on existing proven NVM cell structures are discussed in this dissertation. These solutions, which maintain the advantages of original NVM cells, can be directly used for high reliability requirement products without any special process tuning or control.
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