On the Thermal Performance Analysis of Three-dimensional Chip Stacking Electronic Packaging with Through Silicon Vias

碩士 === 國立清華大學 === 動力機械工程學系 === 101

Bibliographic Details
Main Author: 黃子晉
Other Authors: 陳文華
Format: Others
Language:zh-TW
Published: 2013
Online Access:http://ndltd.ncl.edu.tw/handle/93131981971597301077
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spelling ndltd-TW-101NTHU53110672015-10-13T22:29:57Z http://ndltd.ncl.edu.tw/handle/93131981971597301077 On the Thermal Performance Analysis of Three-dimensional Chip Stacking Electronic Packaging with Through Silicon Vias 含矽穿孔三維晶片堆疊電子構裝之散熱效能分析 黃子晉 碩士 國立清華大學 動力機械工程學系 101 陳文華 鄭仙志 2013 學位論文 ; thesis 69 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立清華大學 === 動力機械工程學系 === 101
author2 陳文華
author_facet 陳文華
黃子晉
author 黃子晉
spellingShingle 黃子晉
On the Thermal Performance Analysis of Three-dimensional Chip Stacking Electronic Packaging with Through Silicon Vias
author_sort 黃子晉
title On the Thermal Performance Analysis of Three-dimensional Chip Stacking Electronic Packaging with Through Silicon Vias
title_short On the Thermal Performance Analysis of Three-dimensional Chip Stacking Electronic Packaging with Through Silicon Vias
title_full On the Thermal Performance Analysis of Three-dimensional Chip Stacking Electronic Packaging with Through Silicon Vias
title_fullStr On the Thermal Performance Analysis of Three-dimensional Chip Stacking Electronic Packaging with Through Silicon Vias
title_full_unstemmed On the Thermal Performance Analysis of Three-dimensional Chip Stacking Electronic Packaging with Through Silicon Vias
title_sort on the thermal performance analysis of three-dimensional chip stacking electronic packaging with through silicon vias
publishDate 2013
url http://ndltd.ncl.edu.tw/handle/93131981971597301077
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