| Summary: | 碩士 === 國立中山大學 === 電機工程學系研究所 === 101 === In this thesis, we present a novel CMOS inverter with simple process and high integration density. The novel CMOS inverter exploit vertical transistor can improve packing density, when compared with the planar CMOS inverter. We focus on the investigation of novel vertical TFT-CMOS trends. In addition, we also design a planar CMOS for comparison.
According to the simulations, the logical characteristics of our proposed CMOS are valid, in which the average propagation delay time is improved 40 % compared with the planar CMOS. That are due to the ION is improved 21 % with the source overlap and the parasitic capacitance is improved 18 % with the drain underlap. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, both p-channel and n-channel devices require only one lithographic step to form the source overlap and drain underlap. The layout area can be significantly decreased 47.4 %, in comparison with the conventional CMOS.
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