Study of Vertical MOSFET with Embedded Oxide

• Main Authors: Shu-huan Syu, 許書桓
• Other Authors: Jyi-Tsong Lin
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/23781086895418462222

碩士 === 國立中山大學 === 電機工程學系研究所 === 101 === In this thesis, we propose a junction vertical MOSFET with embedded oxide (EO JVFET) and an junctionless vertical MOSFET with embedded oxide (EO JLVFET). We find out that the EO can improve the series resistances and drive current compared with vertical SOI device. According to the numerical simulation, we can find out that the subthreshold swing, DIBL and on / off current ratio (Ion / Ioff) of the EO JVFET can be respectively improved 10.5 %, 15.7 % and 20.6 % compared with the junction vertical MOSFET with bulk silicon structure (Bulk JVFET). We also find out the Gm / Id of the EO JVFET can be improved 14.6 % compared with the Bulk JVFET. Therefore, it is believed that based on the design requirements, the optimizations can be readily implemented through EO design in a vertical transistor structure. In addition, we focus on the electrical characteristics of the JVFET and JLVFET through computer simulations. According to the numerical simulation, we can find out that the drive current, subthreshold swing and DIBL of the JVFET can be respectively improved 58.1 %, 6.15 % and 12.8 % compared with the JLVFET. So the JVFET has better short channel behavior. We also find out the transconductance (Gm), Gm / Id and unity gain frequency (fT) of the JVFET can be respectively improved 30.25 %, 42 % and 28.4 % compared with the JLVFET. In other words, it is believed that based on the design requirements, the EO JVFET is still considered as a candidate for future CMOS scaling.