Characterization of III-V Compound Semiconductor MOSFETs with Titanium Oxide and Silicon Oxide Stacked Layers as Gate Oxide

• Main Authors: Wei-hau Chang, 張洧豪
• Other Authors: Ming-Kwei Lee
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/e33xv9

碩士 === 國立中山大學 === 電機工程學系研究所 === 101 === Due to the high electron mobility compard with Si, much attention has been focused on III-V compound semiconductors (gallium arsenide (GaAs) and indium phosphide (InP)) high-speed devices. The high-k material TiO2 not only has high dielectric constant (k =35-100) but has well lattice match with GaAs and InP substrate. Therefore, titanium oxide (TiO2) was chosen to be the gate oxide in this study The major problem of III-V compound semiconductor is known to have poor native oxide on it leading to the Fermi level pinning at the interface of oxide and semiconductor. The C-V stretch-out phenomenon can be observed and the leakage current is high. The higher dielectric constant of poly-crystalline SiO2 film grown on GaAs can be obtained by atomic layer deposition (ALD). But the high leakage current also occurred due to the grain boundary and defects in the poly-crystalline TiO2 film. The surface passivation of GaAs with (NH4)2S treatment (S-GaAs) could prevent it from oxidizing after cleaning and improve the interface properties of MOSFET. The fluorine from liquid phase deposited SiO2 solution can passivate the grain boundary of poly-crystalline ALD-TiO2 film and interface state. The high dielectric constant and low leakage current of fluorine passive ALD-TiO2/S-GaAs can be obtained. The leakage current densities are 3.78 x 10-8 A/cm2 and 2.49 x 10-7 A/cm2 at ±1.5 MV/cm, respectively. The Dit is 4.6 x 1011 cm-2eV-1 at the midgap. The dielectric constant can reach 52.