Implementation of Low Power Multi-Port Memory and It’s Applications in Graphic Processing Units

• Main Authors: Pu-Cheng Wu, 吳普誠
• Other Authors: Shen-Fu Hsiao.
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/74306000854642032076

碩士 === 國立中山大學 === 資訊工程學系研究所 === 101 === Memory design plays an important role in current system-on-chip (SoC) design because memory takes a significant portion of total area. As the complexity of processor cores increases, the support of multiple read/write ports becomes an important issue in memory design. Although current commercial standard cell library usually support multi-port memory generators, they are not very efficient in many SoC design and the number of supported read/write ports usually do not satisfy system requirement. Another important issue in memory design for portable systems is the leakage power which is becoming a critical issue in advanced process technologies. In this thesis, we present a low-leakage multi-port SRAM design and apply it to the design of register files in the vertex shader processor for 3D graphics applications. The multi-port SRAM design uses single-end read/write circuit to reduce area, hierarchical decoding to reduce dynamic power, and some additional circuits to reduce static leakage power. The proposed multi-port SRAM design is integrated with the vertex shader processor using mixed-signal design flow.