| Summary: | 碩士 === 國立中山大學 === 資訊工程學系研究所 === 101 === Small Delay Defect (SDD) is one kind of the signal transition delay faults. It could not be detected via traditional delay testing method because the delay time is too small, however, the-se faults could cause timing failure in the circuit when the accumulation of delay time along the paths is too much.
Typical SDD testing uses commercial ATPG Tools, generating SDD test patterns to detect. Since the delay time of SDD is too small, SDD exists too much in the circuit. Thus, SDD has to sensitize more paths to generate SDD test patterns during test pattern generation and too much CPU runtime.
Using commercial ATPG Tools for SDD testing, it has to consider delay information in the circuit by static timing analysis (STA) tools. However, there are false paths in the circuit, which makes delay time calculation much more pessimistic and leads to unnecessary SDDs.
The thesis proposed the method to detect the false paths during timing analysis to exclude the false paths and redundant faults, and meanwhile to apply statistical static timing analysis (SSTA) to calculate timing instead of STA in order to reduce SDD count and pattern count.
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