Design of Reconfigurable Digital Filters for Tolerating Multiple Timing Errors

• Main Authors: Jia-Wei Jian, 簡嘉韋
• Other Authors: Hsin-Chou Chi
• Format: Others
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/43492701971268492948

碩士 === 國立東華大學 === 電機工程學系 === 101 === As the feature size of chips shrinks with semiconductor technology advancing, the size of transistors and their operating voltage keep decreasing. One of the major problems with advanced semiconductor technology is timing errors caused by process variation and device aging. With such problems, conventional worst-case designs suffer poor system performance. This thesis proposes an aggressive design technique for VLSI digital filters for tolerating multiple timing errors. We have developed a methodology of designing reconfigurable VLSI digital filters that can tolerate multiple timing errors. The reconfigurable digital filters are resilient to any timing errors occurring at any stage and any time. When the timing error occurs, the system reconfigures the buffer cells of digital filters with little performance degradation. We have applied the technique to two example digital filter designs, including an FIR filter and an IIR filter. The implementation results show that our proposed designs achieve tolerance of multiple timing errors with reasonable cost.