Low Leakage Clock Tree Design Using Reconstructed Buffers of a 22nm Standard Cell Library

Low Leakage Clock Tree Design Using Reconstructed Buffers of a 22nm Standard Cell Library

碩士 === 國立彰化師範大學 === 電子工程學系 === 101 === In recent ten years, the development of semiconductor manufacturing has gradually grown in complexities and power consumption of VLSI chips. Thus leakage power reduction technology has become more important as in some cases leakage power of advanced nanometer p...

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Bibliographic Details
Main Authors:	Meng-Lin Hsieh, 謝孟霖
Other Authors:	Tsung-Yi Wu
Format:	Others
Language:	zh-TW
Published:	2013
Online Access:	http://ndltd.ncl.edu.tw/handle/38626204370355349889

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