Low Leakage Clock Tree Design Using Reconstructed Buffers of a 22nm Standard Cell Library

• Main Authors: Meng-Lin Hsieh, 謝孟霖
• Other Authors: Tsung-Yi Wu
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/38626204370355349889

碩士 === 國立彰化師範大學 === 電子工程學系 === 101 === In recent ten years, the development of semiconductor manufacturing has gradually grown in complexities and power consumption of VLSI chips. Thus leakage power reduction technology has become more important as in some cases leakage power of advanced nanometer processor chips was found to exceed its dynamic power. In this paper, we use Buffer Circuit Optimization Program in our lab to redesign the 22nm standard cell library for constructing the clock tree. Our results show that leakage is obviously reduced while buffer transfer delay time is not obviously increased. We also design low leakage H-type clock tree by the reconstructed buffer to test the buffer performance. The Spice Circuit of the original 22nm buffer cell for is minimized version of the NanGate 45nm buffer standard cell. A NanGate buffer has two inverters, area of which at input is small while that at output is large. It uses HSPICE simulation that when the width of NMOS transistor at inverter input is increased to some factor and that the width of PMOS transistor at inverter output is decreased to some factor, buffer leakage is obviously reduced. Berkeley Predictive Technology Model (BPTM) of 22nm technology was used for Buffer Circuit Optimization Program. Consider CLKBUF_X2 buffer standard cell. It is calculated by the optimization program that when the width of NMOS transistor at inverter input is increased to a factor of 1.29 and that the width of PMOS transistor at inverter output is decreased to a factor of 0.6 compared with the original, leakage for the reconstructed buffer is minimized. The maximum and average leakage for the original and new reconstructed CLKBUF_X2 are reduced from 44nA and 39nA to 33nA and 32nA, accounting for a 25% reduction for maximum leakage and 18% reduction for average leakage. Buffer Circuit Optimization Program ensures rising/falling delay time difference between the new reconstructed circuit and the original circuit to be within 2% . Low leakage buffer can be used to build H-type clock tree. In one of our experiments on a 262144-leaf-node H-type clock tree, 20% of maximum leakage and 15% of average leakage can be reduced with merely 2% increase of delay time if using low leakage buffer in replacement of the original buffer.