A Low Power Dual-clock FIFO for Data Transfers Between Unrelated and Haltable Clock Domains

• Main Authors: Hsu Chih-Chia, 許智嘉
• Other Authors: Wei Kai-Cheng
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/80644465550079786485

碩士 === 國立彰化師範大學 === 資訊工程學系 === 101 === A multi-clock system is more common use in the system-on-chip (SOC) design which divid the circuit into several blocks, there are independent function, different clock domain and phase with each other. The main problem of this design is how to transfer the data between different blocks robustly. The major issue is the metastability which will reduce the throughput of data transmission between domains. To solve this problem, we proposed a robust and power efficient dual-clock first-input first-out (FIFO) architecture that uses gray code to transferring data between different clock domains. Using the write and read flags, the system can be guaranteed that the full and empty detectors will work correctly. We replaced the original adder to reach low power consumption and high throughput. The proposed architecture also deleted the decoder which transform the Gray Code back to the binary code representation, and by this way, we can reduced the area overhead of the circuit. The design was synthesized using Synopsys Design Compiler with TSMC 0.18μm standard cell process. Compared with previous dual-clock FIFO, the area, dynamic power consumption, and the static power consumption can be reduced from 4% to 8%, 15% to 25%, and 8% to 12%, respectively. The proposed design also can read the more data from 3% to 17% than the original architecture .