The Design of Robust FIFO Interface for Multiple Clock Systems
碩士 === 國立彰化師範大學 === 資訊工程學系 === 100 === A multiple-clock system is a commonly used method for meeting the tight power budgets in a system-on-chip design. The whole circuit is partitioned into several function independent sub-blocks[1]. These sub-blocks are operated under their suitable clocks. Com...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/64671589359377020978 |