High-Throughput Turbo Decoder Design with New Interconnection Network for LTE/LTE-A System

• Main Authors: Tsao-Hsuan Lee, 李肇軒
• Other Authors: Pei-Yun Tsai
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/87123179754476132422

碩士 === 國立中央大學 === 電機工程學系 === 101 === In this paper, we design and implement a high-throughput turbo decoder for the 3rd Generation Partnership Project (3GPP) Long Term Evolution-Advanced (LTE-advanced) system. To support the high data rate, we adopts eight radix-4 parallel soft-in/soft-output MAP decoders. We adopt MAP decoding with sliding window mechanism to decrease decoding time. And we also use the warm-up scheme to compensate the performance loss. Besides, The properties of quadratic permutation polynomial (QPP) interleaver are exploited to reduce the complexity of the switch network between memory and MAP decoder. Four techniques are used to improve the hardware design. First, the in-place algorithm is adopted to decrease the size of α-memory in MAP decoder , and hence the overall area can be reduced. Next, the processing periods of the last window in the first half iteration and the first window in the second half iterations are scheduled to be overlapped, Consequently, the decoding time is reduced and the throughput of the turbo decoder can be enhanced. The interconnection network is designed elaborately. A new interconnection network is proposed with a simple rotator and control logic. Using simple conditional judgement with extra multiplexers to exchange the address and memory data, we can support parallel processing of the turbo decoding. In addition, We achieve non-conflict memory access under high parallel and high radix hardware design for 188 modes . From synthesis result, this work can operate at 406 MHz to offer decoding data rate up to 511 Mbps in 90nm CMOS technology.