App-CABC: Applications of the Yield-aware Capacitor Array Block Creator
碩士 === 國立中央大學 === 電機工程學系 === 101 === As the device shrinking of semiconductor process, the process variation causes the mismatch and wire parasitic effect between elements becomes much more seriously. It also causes high complexity and time-consuming on design circuits. Therefore, layout automation...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/09791197414621315175 |