| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 101 === As the evolution of semiconductor process technology from 0.18um, 90nm to the present minimum is 22nm, the process variation will be more and more serious in device mismatch. This represents the analog circuit design increase time-consuming and high complex, then layout automation is likely to play a key role in analog circuit design. The performance of many types of analog circuits, like ADC, DAC, filter, etc., relies on the implementation of accurate capacitor array ratios. In order to reduce the negative effects, designers are determined by properly arranging the identical unit-size capacitors and used spatial correlation to decrease the effect of process variation. Among them, how many unit-size capacitor you want to cut and how to assign the capacitance in capacitor array has become a very important part with automatic layout assignment.
In this thesis, we propose a layout assign method a yield-aware placement with power-of-two cutting and weighted priority for capacitor array block creator. We place by changing the priority of capacitor according to different circuit constraints, the placement will be place in a better result. And we have established a power-of-two matrix structure, and propose a power-of-two capacitance cutting method. Used this method in the capacitor placement can achieve high dispersion, less time-consuming and the accuracy of capacitor array layout. Finally, we cite a few different placements to illustrate the impact of placing the array. For a particular circuit, various assignment capacitor arrays are validated by their circuit yield, which is done by Monte Carlo method. The results show the matching of capacitor ratio increased and the circuit yield enhancement.
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