| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 101 === For a transceiver in wireless communication, the low phase noise local oscillator (LO) source is an indispensable element, since it is an important issue for designing a high-frequency and low phase noise LO source is an important issue. The phase-locked loop (PLL) is one of the methods to stabilize the output frequency of the voltage-controlled oscillator (VCO). In order to provide system with a stable and low phase noise LO source for the microwave and millimeter wave (MMW) system, an injection-locked technique can be adopted to enhance the operation frequency for many active circuits, such as oscillator, frequency divider, PLL, and frequency multiplier. A key building block in the LO source is the VCO with quadrature outputs. The quadrature VCO (QVCO) is needed for I/Q modulation or demodulation.
In Chapter 2, three K-band differential VCOs, including a conventional common-base VCO, a cascode commom-emitter VCO and a conventional commom-emitter VCO with active load, have been designed using WIN Semiconductors 0.5-μm PHEMT and 2-μm HBT technology. The negative resistance of the HBT-HEMT cascode VCO is analyzed. The tuning bandwidth of the differential VCOs are 38.3%、22% and 31.3%. The CB differential VCOs demonstrates the widest bandwidth among the relevant literatures.
The design and analysis of an injection-locked oscillator (ILO) is presented in Chapter 3. Simulated normalized third harmonic currents of the frequency pre-generator as a function of base current, and select the base current for higher frequency conversion efficiency while maintaining oscillation. The ILO with a locking range of 1.4 GHz is realized using TSMC 0.18-μm SiGe BiCMOS process. The measured maximum output frequency is 18.37 GHz.
In the Chapter 4, we used TSMC 90-nm CMOS process to realize a K-band VCO with transformer-feedback and gate-modulation techniques. The analysis for generating quadrature is presented in detailed manner.The measured oscillation frequency is from 23.4 to 25.1 GHz. The measured phase noise is －98.6 dBc/Hz at 1-MHz offset. The dc power consumption is 16.15 mW and the RF output power is －9.6 dBm. The minimum I/Q phase and amplitude error are 0.28° and 0.55 dB, respectively. The VCO demonstrates a figure of merit (FOM) of －174.4 dBc/Hz.
The analysis and design of the ILFD are presented in Chapter 5. The divide-by-6 ILFD with a locking range of 1.1 GHz is fabricated using TSMC 0.18-μm CMOS process. Moreover, the proposed ILFD is applied to a fully integrated PLL, and the measured frequency of the PLL is from 22.09 to 22.19 GHz. The measured phase noise with injection signal is −130 dBc/Hz at 1 MHz offset. The dc power consumption is 102 mW. The inection-locked technique is used to improve the phase noise of the PLL. The conclusion is given in Chapter 6.
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