SERL: Soft Error Resilient Latch Design 研究生：張竣惟 指導教授：溫宏斌 中 華
碩士 === 國立交通大學 === 電機工程學系 === 101 === As transistor size continues to shrink, VLSI circuits become more and more susceptible to the soft errors induced by adiation particle strike. Soft error occurs when a transient pulse propagates to a memory cell and gets latched to incur a single event transient...
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37887897751110574738 |