SERL: Soft Error Resilient Latch Design 研究生：張竣惟 指導教授：溫宏斌 中 華

• Main Authors: Chang, Chun-Wei, 張竣惟
• Other Authors: Wen, Hung-Pin
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/37887897751110574738

碩士 === 國立交通大學 === 電機工程學系 === 101 === As transistor size continues to shrink, VLSI circuits become more and more susceptible to the soft errors induced by adiation particle strike. Soft error occurs when a transient pulse propagates to a memory cell and gets latched to incur a single event transient (SET) or to flip the value stored in memory cell, to incur a single event upset (SEU). Soft errors can cause system failure and unpredictable erroneous condition. In order to eliminate soft errors, previous researches have proposed different DFF rchitectures for SER protection. One of the state-of-the-art designs is BISER, which protects designs against SET and SEU, simultaneously. However, BISER adds more transistors to the original DFF resulting in more area overhead and higher probability of soft error. Therefore, we propose a soft error resilient latch (SERL) which has less area overhead and offers better SER protection. Combined with regular latches, SERL-DFF can use the same delay time to eliminate more soft errors than BISER does. Experimental results show that SERL-DFF has 20% more SER reduction than BISER at the device and system level and uses 7% less area than BISER. As a result, SERL-DFF is effective in eliminating SERs in sequential circuits and only has a small area overhead.