| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 101 === The proposed 0.5-V monitoring system detects and quantifies the data jitter. In the meantime, it recovers data as well. The digital circuit transmits the NRZ data, and its supply voltage is scaled by this monitoring system. Consequently, data jitter can meet the systematic specification with minimized voltage. The proposed system can be divided into three parts: the digital circuit (DUT), the self-tuning dynamic voltage scaling system (STDVS), and the phase-locked loop (PLL). The DUT in this system is used to transmit NRZ data. The STDVS system consists of two connected loop, DVS and CDR loop. One is to optimize the supply voltage of the DUT circuit, and the other is to recover the NRZ data transmitted by the DUT circuit from jitter, respectively. The PLL generates multi-phases to achieve the two mentioned function of the STDVS system.
The chip is fabricated in TSMC MSG 90nm CMOS technology. The total silicon area is 1mm2, including buffers and PADs. With jitter requirement of 4/16UI, the 0.5-V STDVS system consumes 73.5W at 40MHz. The data jitter of the DUT circuit is 5.61ns and the recovered data jitter of the CDR is 1.94ns. The power consumption of the 0.5-V PLL is 155W, and the VCO’s peak-to-peak jitter is 186.87ps. The DUT circuit can be operated within the voltage range from 0.24V to 0.42V. Compare to 0.5V, the power consumption of the DUT operated at 0.34V is reduced to 55.62% with jitter requirement of 4/16UI. This STDTVS scheme results in energy savings efficiency from 31.48% to 74.97%.
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