The Design and Implementation of a Power-Efficient Bio-Signal Processing System-on-Chip for Epileptic Seizure Detection

• Main Authors: Chen, Tsan-Jieh, 陳燦杰
• Other Authors: Chiueh, Herming
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/stn794

博士 === 國立交通大學 === 電信工程研究所 === 101 === In recent years, integrated circuits play an important role in today’s personal medical applications. These medical devices are usually battery-powered and their limited power budget imposes design challenges on signal acquisition and processing. Epileptic seizure control is one of the emerging applications. In this application, closed-loop neurostimulation is the most important method for seizure control devices. A real-time seizure detector is the kernel of a closed-loop seizure controller. In this dissertation, several low-power high-performance techniques from software to hardware level are applied for real-time power-efficient seizure detection. To demonstrate the proposed ideas, three works are designed and implemented. Long-Evans rats with spontaneous absence seizures are used as animal models for long-term continuous verification. In the first work, a bio-signal processor (BSP) core based on 32-bit reduced instruction set computer (RISC) architecture for seizure detection is implemented to achieve low-power consumption and continuous real-time processing. The proposed BSP core consists of 5-stage integer pipeline, 32×32 multiply-accumulator (MAC) unit, and a 32-bit tick timer. These features can enable high-performance signal processing and task scheduling for many biomedical applications. The floating-point seizure detection algorithm is approximated and rescheduled for short latency. The high-performance BSP core is implemented in 0.18 ?慆 complementary-metal-oxide semiconductor (CMOS) technology to verify functionality and capability. The measurement results show that the implemented processor can reduce over 90% power consumption compared with our previous prototype, which is implemented on an enhanced 8051 microcontroller. In the second work, a power-efficient BSP based on the first work is proposed to utilize for diverse physiological signals. Tens of kilobytes memory is embedded for efficient program execution in the proposed processor. The multi-mode analog-to-digital converter (ADC) is also integrated for physiological signals acquisition. Several serial and parallel ports are integrated with RISC processor for system expansion. Significant performance improvement is achieved through instruction optimization. Voltage and frequency scaling as well as clock gating are applied to reduce dynamic power on this work. The proposed BSP is implemented in 0.18 ?慆 CMOS technology. The measurement results show that the BSP consumes hundreds of microwatts to perform real-time seizure detection. The highly integrated and power-efficient BSP can be applied for excessive portable medical devices. The last work presents a power-efficient seizure detection system-on-chip (SoC). The FFT and entropy coding engines with direct memory access (DMA) feature are designed to reduce dynamic power through high-performance computation. The sample buffer and data control unit for signal acquisition is proposed to reduce context switching overhead. The seizure detection SoC is implemented in 0.18 ?慆 CMOS technology. The simulation results show that the implemented SoC consumes tens of microwatts to perform real-time seizure detection. The ultra-low power consumption of the proposed SoC enables implantable closed-loop seizure suppression in the future. Combining with efficient hardware architecture and software optimization, the real-time processing capability, design flexibility, portability, and versatility of the proposed platform and its design methodology can be applied on closed-loop seizure controller and many biomedical implants.