| Summary: | 碩士 === 國立交通大學 === 電信工程研究所 === 101 === This paper presents a fully digital binary-phase-shift keying (BPSK) demodulator for data and power telemetry. This demodulator recovers BPSK signals by detecting the symbol edge of the digitized received carrier. Parameters of the coupling coils, rectifier DC output, and data rate are taken into consideration in the early design stage. The demodulator achieves a data rate of 13.56Mb/s at a carrier frequency of 13.56MHz, achieving 100% data rate to carrier frequency ratio. Given a limited coil size and quality factor, the maximum data rate of this system achieves 678kb/s with BER < 10-9. Fabricated in a 0.18μm CMOS process, the chip area is 0.445mm2. The chip core dissipates 191μW at 13.56MHz. A system prototype was developed to transmit data and power simultaneously through a pair of coils.
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