TSV and micro-bump co-planning for 3D IC manufacturing yield improvement
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 101 === In 3D IC, manufacturability is dominating the importance among all design factors. In order to cope with micro-bump failure during manufacturing, in this research, we propose a TSV and micro-bump co-planning methodology and a new 3D IC design flow. We first...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/33848690000966662671 |