TSV and micro-bump co-planning for 3D IC manufacturing yield improvement

• Main Authors: Fu, Tien-Lung, 富天龍
• Other Authors: Chen, Hung-Ming
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/33848690000966662671

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 101 === In 3D IC, manufacturability is dominating the importance among all design factors. In order to cope with micro-bump failure during manufacturing, in this research, we propose a TSV and micro-bump co-planning methodology and a new 3D IC design flow. We first generate TSV island modules as our TSV “cell” library. Next, we use a dynamic programming based algorithm to determine the combinations of TSV island modules for TSV area minimization. Results show that with 100% micro-bump doubling rate, we utilize less area compared with intuitively adding micro-bumps. In all, our approach not only improves the yield of 3D IC, it also effectively utilizes die area.