| Summary: | 博士 === 國立交通大學 === 電子工程學系 電子研究所 === 101 === This thesis presents background calibration techniques to reshape the capability of
noise shaping of discrete-time (DT) Delta-Sigma modulators (DSMs). The calibration
can operate in the background without interrupting the normal operation of the DSM. The
proposed scheme relaxes the requirement of opamp DC gain in a DT DSM. and relaxes
the matching requirement in a cascaded-DSM.
The opamp in a DT DSM is requested to sacrifice the DC gain for wide-band applications.
This induces the issue of integrator-leakage and a degraded signal-to-noise-anddistortion
ratio (SNDR). We develops an integrator-leakage calibration technique for a
DT DSM. In the calibration of an integrator, its integration leakage is determined in the
digital domain, and the leakage compensation is applied to the same integrator in the analog
domain. The proposed scheme can be used to calibrate all of the integrators in a DT
DSM of any form. The developed scheme can relax the requirement of opamp DC gain
in the high-speed high-resolution DT DSMs.
A cascaded DSM without the perfect matching between analog loop filters and digital
noise cancellation filters exhibits a degraded SNDR due to noise leakage. We develops
an noise-leakage calibration technique with low-complex circuits. The noise leakage is
determined by injecting an out-of-band signal, and the leakage is eliminated by merely
adjusting the gain of digital filter. The developed scheme can relax the matching requirement
in the cascaded DSMs and accomplish the higher-order noise shaping.
A 2-2 cascaded discrete-time DSM is fabricated in a 65 nm CMOS technology. Each
stage of DSM consists of two integrators realized the low gain high speed opamp. The
integrator leakage originated in the first stage is reduced by integrator leakage calibration
at first. Then, the mismatch between the analog loop filter and the digital noise cancellation
filter is cured by noise leakage calibration. The proposed calibrations enable the
modulator to perform the high-speed high-resolution analog-to-digital conversion.
The active area of the fabricated DSM is 0.58x0.33 mm2. This cascaded DSM with
open-loop opamp gain of 20 dB is operating at 1.1 GHz clock rate. Its OSR is 33 and its
bandwidth is 16.67 MHz. The DSM consumes 94mW from 1.0 V power supply. Before
activating the calibrations, the SNDR is 54 dB and the dynamic range (DR) is 60 dB.
After activating the integrator leakage calibration and the noise leakage calibration, the
SNDR becomes 74 dB and the DR becomes 81 dB. The figure-of-merit of the DSM is
163.5 dB.
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