| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 101 === Latency-constrained memories are utilized for the high throughput systems. As the memory
process is scaling down, error control codes are used to improve reliability. In the thesis,
a double error correcting (DEC) BCH codec is designed for latency-constrained memory
systems such as NOR flash memories. To meet the design target of latency-constrained
memory systems, the fully parallel architecture with huge hardware cost is utilized to process
both the encoding and decoding scheme within one clock cycle. Since the BCH encoder and
decoder will not be activated simultaneously in NOR flash applications, we combine the
encoder and syndrome calculator based on the property of minimal polynomials in order
to efficiently arrange silicon area. Furthermore, we developed two new expressions of error
location polynomials based on matrix operations to reduce the number of constant finite filed
multipliers (CFFMs) in Chien search, which dominates the hardware complexity of decoder.
According to 90 nm CMOS technology, our proposed DEC BCH codec with 256-bit data
length can achieve 2.5 ns latency with 14,789 gate count by using our first proposed method,
whereas the second approach can achieve 2.5 ns latency with 12,484 gate count.
|
|---|
