| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 101 === Disparity estimation is one of the most interesting and important research topics in the field of stereo TV application. Accurate estimation of disparity can significantly improve the visual experience on the stereo image but at the expense of noticeable computational complexity consumptions.
In this thesis, several techniques are proposed to improve the accuracy of estimated disparity results at a low memory cost. The edge detection algorithm is first adopted in the proposed algorithm to derive the important image content features and edge information for making the upcoming disparity estimation process gets more precise results. Afterwards, the proposed disparity propagation will take the edge information both from vertical and horizontal direction into account for deciding whether the disparity should be propagated from the edge area to the texture-less area. After the disparity propagation phase, the un-propagated pixels will be treated by our proposed dual-way dynamic programming method for determining their disparities. In our proposed dual-way dynamic programming algorithm, the edge information will be taken into account as the energy minimization factor which will affect the results of the estimated disparity. In addition, several post processing techniques including occlusion handling, directional region voting, and edge-based temporal consistency are also adopted in this thesis to further improve the estimated disparity results with considering edge information.
Simulation results demonstrate that our proposed disparity estimation algorithm not only improves the accuracy of the estimated disparity but also achieves less computational complexity consumptions and memory buffer requirements. On average, our proposed algorithm can achieve 34.48dB PSNR and reduce average 53.08 % of computation cost compared to the conventional dynamic programming method. Finally, the proposed algorithm is implemented in hardware form at 1920x1080@90fps and the synthesized gate count of our design is only 2,325K by using 90nm CMOS technology.
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