Study on the High-Performance Poly-Si Thin Film Transistors for the Applications in Three-Dimensional ICs and System on a Panel

• Main Authors: Lee, I-Che, 李逸哲
• Other Authors: Cheng, Huang-Chung
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/48245123816393889260

博士 === 國立交通大學 === 電子研究所 === 101 === High-performance polycrystalline silicon thin film transistors (poly-Si TFTs) have been studied for the applications in three-dimensional integrated circuits (3-D ICs) and system on a panel (SOP). Several approaches were proposed to enhance the performance of the poly-Si TFTs, which was explained by the proposed mechanisms with device simulations. At first, the bottom-gate (BG) poly-Si TFTs were studied in virtue of metal-induced crystallization (MIC) and excimer-laser crystallization (ELC). In case of MIC, while increasing the active thickness increased and/or shrinking the dimensions, the electrical characteristics could be improved but the device-to-device uniformity was degraded. A possible mechanism based on the lateral and vertical grain growth was proposed to explain the effects of the device dimensions and active layer thickness of the BG poly-Si TFTs with MIC. On the other hand, the BG poly-Si TFTs with ELC exhibited better electrical characteristics than the devices with MIC due to the large lateral grains in the channel under appropriate laser irradiation energy density. Then, a novel oxide step structure with ELC was also proposed to produce large lateral grains in the channel region and, therefore, the single-gate oxide-step poly-Si TFTs could achieve high field effect mobilities above 300 cm2/V-s and 150 cm2/V-s for n-channel and p-channel TFTs, respectively, which were about 2.5 times higher than that of the conventional excimer-laser crystallized devices. Moreover, both the performance and uniformity were significantly improved for the oxide-step poly-Si TFTs in stead of the conventional ones as the dual-gate structure was introduced owing to avoiding of the single one perpendicular grain boundary. The BG poly-Si TFTs with gate-dielectric stack of oxide, nitride, and oxide crystallized via ELC were applied to demonstrate high-performance two-bit SONOS-type non-volatile memory. By means of channel-hot-electron injection(CHEI) and band-to-band hot hole injection (BBHHI), the program/erase speed of the BG SONOS TFTs with ELC were about 100 time faster than those of the devices with solid-phase crystallization (SPC) owing to their high field effect mobilities. To further multiply the storage density, the high-performance SONOS TFTs with double-gate structure (DG) have been also achieved to exhibit four bits per cell via simple ELC method. Since the DG SONOS TFTs with ELC have two channels, namely top and bottom channel, the 4-bit per cell was implemented by storing two bits in each channel. The experiment results demonstrated a memory window of 2.89 V with ignorable lateral and vertical interferences because of the CHEI program and partial depletion of channel for the DG SONOS TFTs. Moreover, the gain boundary protrusion can be formed the ELC, and, therefore, the electric field was enhanced near the protrusion. In the study of the grain boundary effects on the memory characteristics, the single one grain boundary protrusion in the channel was achieved by means of the recessed-channel (RC) SONOS TFTs with ELC. As the artificially controlled grain boundary located in the middle of channel, the memory characteristics of the RC-ELC SONOS TFTs were better than those of the SONOS TFTs with conventional ELC and SPC due to the enhancement of electric field near the grain boundary protrusion. On the contrary, when the artificially controlled grain boundary was located near one side junction, the memory characteristics differed from the grain boundary near drain junction and near source junction. After programming, a larger memory window was found in the device with one grain boundary near source junction as compared with the device with one grain boundary near drain junction. A series of device simulation was studied to support the mechanism that the total potential barrier height caused by the grain boundary and programmed charge was lowered more in the drain junction than in the source junction. In addition, the poly-Si TFTs with ELC were applied to three-dimensional integrated circuits (3-D ICs) applications. Two novel and simple 3-D structure with vertically-stacked complementary devices using ELC were proposed. The first type of 3-D CMOS inverter with ELC, which is composed of one BG poly-Si TFT with single one perpendicular grain boundary in the channel on the lower layer and one stacked top-gate (TG) poly-Si TFT on the upper layer, the electrical properties were better than those with SPC. To further improve, the second type of 3-D CMOS inverter with ELC, which is composed of BG poly-Si TFTs with single one perpendicular grain boundary on both layers, could achieve higher mobility about 400 cm2/V-s and 180 cm2/V-s for n-channel and p-channel devices, repectively. In addition, while compacting the separation oxide thickness, the output current of the devices on the lower was tend to be increased owing to the double-gate effect, which was verified with a device simulation. In summary, high-performance poly-Si TFTs have been developed to be potential to the applications in 3-D ICs and SOP. The parameters that affected the performance of poly-Si TFTs, non-volatile memory, and 3-D ICs were discussed in detail.